Ship better silicon, faster—without adding headcount.

Situation: A startup was building an application-specific processor SoC but was blocked on physical implementation: placement-and-routing (P&R) could not converge to a clean signoff state (timing closure, power signoff, shorts-free routing, and passing DRC/LVS/ERC).

What We Did (2 weeks):

• Drove timing closure by iterating on floorplan/layout changes and providing SDF-based timing feedback to the RTL team.
• Planned and corrected the power grid so it did not produce power violations and integrated with IP blocks seamlessly.
• Integrated placeholder/black-box (“ghost”) IP blocks to unblock physical verification and enable clean Calibre runs.
• Resolved a backlog of electrical-rule and LVS issues, tightening the loop between implementation and verification.
• Worked in a tight iteration cadence, often delivering actionable feedback by the team’s next workday and re-running updated RTL/netlists multiple times per day.

Outcome: Within two weeks, the design reached a stable P&R and signoff-ready state and the team hit their MPW submission deadline (TSMC) with all checks passing. A few months later, they reported fully working silicon and shared a working PCB as a thank-you.

Situation: A major semiconductor company needed an automated “cross-view validation” tool to catch inconsistencies across library deliverables (cell sets, pins, area, shapes) and to support repeatable releases across multiple formats. The tool needed to run on RHEL5 and RHEL6 64-bit hosts.

What We Did (4 weeks):

• Built the Cross View Validation application (core in C++) and delivered it against a customer-provided build VM/toolchain.
• Implemented a configuration-driven workflow to validate one or more library blocks at a time, including optional cellmap support to match cells across libraries with different naming.
• Implemented validation checks described in RS0048-00-01 (examples): Liberty↔LEF/GDSII/Spice/Verilog, LEF↔GDSII, LEF↔LEF, GDSII↔GDSII, plus internal-format checks (e.g., LEF polygon overlap, Spice transistor-name uniqueness).

Outcome: The customer used the tool to validate many ARM and GlobalFoundries libraries, catching cross-format mismatches early and increasing library release confidence.

Situation: At UC San Diego, a research team was running a physical-design flow on an advanced-node library and hit a recurring gap where vendor tools were often brittle or slow: reliable well-tap/endcap insertion and correct row/power-stripe cutting on dense, macro-heavy floorplans with irregular placement constraints. The team needed a robust, fast, scriptable “tapcell” point tool that could generate correct placements and emit an updated DEF for downstream implementation.

Source: github.com/The-OpenROAD-Project/tapcell

What We Did:

• Built a standalone command-line application with a C++17 core placement engine (checkerboard + boundary cell insertion; row cutting/sanitization around fixed instances/obstructions).
• Embedded Tcl design-flow logic into the executable for configuration, scenario execution, and LEF/DEF parsing; optionally enabled Tk for interactive debugging/inspection.
• Exposed the C++ engine to Tcl via SWIG (Tcl wrappers + a small bridge API), keeping algorithmic code in C++ and flow glue in Tcl.
• Added Makefile-based builds and a lightweight test harness; provided a Docker build environment (CentOS6) with explicit toolchain requirements (GCC 8.3+, SWIG 4+, Tcl/Tk headers).
• Integrated placement verification hooks for Cadence Innovus-based checking in downstream flows.

Outcome: TapCell enabled repeatable, automated special-cell insertion and DEF updates on macro-heavy designs. In internal comparisons, it outperformed comparable industry vendor tapcell insertion flows (runtime and robustness on constrained layouts), making it a reliable “last mile” physical implementation utility.

Situation: A telecom SoC team had highly regular datapath structures (replicated slices, buses, and repeated logic motifs) but needed a deterministic way to recognize those patterns in a flat netlist and then drive vendor place-and-route tools with the right layout intent. The goal was to automatically extract regular structures, generate placement groupings/constraints, and produce a layout plan that vendor tools could implement reliably.

What We Did:

• Built a custom datapath placer (“Shelby Datapath Generator”) to load standard design views and build a unified internal model (Liberty + LEF/DEF; optional Verilog/Spice handling for netlist/library validation workflows).
• Implemented pattern/regularity extraction over netlists (instance/pin equivalence, pattern graphs, grouping into rows/columns/grids, and optional hierarchy collapse into modules).
• Generated constraint artifacts consumable by vendor flows (Tcl constraint scripts and Cadence-style datapath/SDP group files) to steer placement of regular structures.
• Provided a Qt-based GUI for schematic/layout inspection plus an embedded Tcl/Tk console for scripting, rapid iteration, and debug.
• Used Flex/Bison parsers for multiple EDA formats and Boost-based utilities/algorithms (filesystem + gzip IO for compressed inputs, geometry/polygon ops, graph routines for quick Steiner approximations, and force-directed refinement).

Outcome: Shelby automated the “regularity to constraints” path: it converted repeated datapath patterns into explicit placement intent (rows/columns/grids) that vendor tools could consume, improving predictability on datapath-heavy blocks and reducing manual, error-prone constraint authoring.

Situation: A fabless semiconductor customer needed a scalable, robust methodology to efficiently share resources beyond tool own parallelism and regressions to run large EDA flows across an SGE grid (and compatible proprietary schedulers): frequent regressions, characterization runs, and many design-space variants with reliable QoR capture. They wanted to produce a reference flow using a well-known SoC design to prove end-to-end execution and grid orchestration. Customer also requested targeted improvements to an existing distributed floorplanning and P&R system used in HPC grid environments.

What We Did:

• Built and validated a distributed foundation flow executed across SGE (and proprietary queue scheduling), including orchestration, dependency management, priority-based preemption, and reproducible run packaging.
• Used a well-known SoC reference design (OpenSPARC) to validate the full flow from synthesis through place-and-route and signoff checks under grid scheduling.
• Added log parsing and QoR metric extraction (WNS/TNS, congestion, routing violations, power, HPWL, per-layer routing length, via counts) to enable automated regressions and design-space exploration.
• Stabilized distributed regressions and build automation, enabling high-volume experimentation without manual oversight.
• Modernized and supported a grid-automated floorplanning/P&R engine used in HPC environments, improving performance, robustness, and regression safety.

Outcome: The customer gained a repeatable distributed flow for large-scale experiments and regressions, with clear QoR metrics dashboard and demonstrable grid execution on a real SoC design. The floorplanning/P&R system became more reliable under distributed workloads, reducing turnaround time and improving flow confidence.